WDPROTECT=THE_WATCHDOG_TIME_OU, WDEN=STOPPED, WDRESET=NORESET
Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer.
| WDEN | Watchdog enable bit. Once this bit has been written with a 1, it cannot be rewritten with a 0. 0 (STOPPED): The watchdog timer is stopped. 1 (RUNNING): The watchdog timer is running. |
| WDRESET | Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be rewritten with a 0. 0 (NORESET): A watchdog timeout will not cause a chip reset. 1 (RESET): A watchdog timeout will cause a chip reset. |
| WDTOF | Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT. Cleared by software. Causes a chip reset if WDRESET = 1. |
| WDINT | Warning interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software. |
| WDPROTECT | Watchdog update mode. This bit can be set once by software and is only cleared by a reset. 0 (THE_WATCHDOG_TIME_OU): The watchdog time-out value (TC) can be changed at any time. 1 (THE_WATCHDOG_TIME_OU): The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. |
| LOCK | A 1 in this bit prevents disabling or powering down the watchdog oscillator. This bit can be set once by software and is only cleared by any reset. |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |